Level shifters are utilized in electronic circuits for changing the voltage of a signal from one voltage level to another voltage level. For example, some electronic circuits employ different power domains, wherein different reference voltages are used to power the circuitry in each power domain. The reference voltage in a power domain defines the voltage levels that represent an asserted logic state (e.g. a logic value of “1”) and a negated logic state (e.g. a logic value of “0”) for signals in the power domain. In order to ensure proper communication of information between power domains, a level shifter can be employed to shift the voltage of a signal communicated across the power domains so that the logic state represented by the signal is consistent over the power domains.
Level shifters are sometimes used in applications where input logic voltage level signals are translated to output signals at higher voltage levels. For example, automotive, electronic data processing, and industrial control applications may require high voltage level shifters to drive various peripheral devices. Such circuits are often implemented in application specific integrated circuits (ASICs) or as independently packaged circuits. High voltage level shifters may translate a logic level (e.g., 0 to 5 volts) input signal to signals at higher voltage levels.
High voltage level shifters having short propagation delay are disclosed herein. In one embodiment, a high voltage lever shifter includes an output driver, a pulse generator, and a high-side gate driver. The output driver is configured to switch a voltage of at least 200 volts. The output driver includes a high-side output transistor. The pulse generator is configured to generate an on pulse at a first edge of an input signal received at an input terminal of the level shifter and to generate an off pulse at a second edge of the input signal. The high-side gate driver is configured to drive the high-side output transistor. The high-side gate driver is coupled to an on pulse signal line that conducts the on pulse and is coupled to an off pulse signal line that conducts the off pulse. The high-side gate driver includes a blocking circuit configured to detect a voltage of the on pulse signal line, to detect a voltage of the off pulse signal line, and to inhibit generation of a drive signal to the high-side output transistor based on a difference of the voltage of the on pulse signal line and the voltage of the off pulse signal line being less than a predetermined amount.
In another embodiment, a transistor driver includes a pulse generator, a blocking circuit coupled to the pulse generator, and a latch coupled to the blocking circuit. The pulse generator is configured to generate an on pulse at a leading edge of an input signal received at an input terminal of the high-side transistor driver and to generate an off pulse at a trailing edge of the input signal. The pulse signal generator is configured to drive an on pulse signal line that conducts the on pulse and to drive an off pulse signal line that conducts the off pulse. The blocking circuit is configured to enable state change of a drive signal to drive a high-side drive transistor based on voltage of the on pulse signal line exceeding a first threshold and voltage of the off pulse signal line not exceeding a second threshold, or voltage of the off pulse signal line exceeding the first threshold and voltage of the on pulse signal line not exceeding the second threshold.
In a further embodiment, a level shifter includes an output driver, a pulse generator, and a high-side gate driver. The output driver is configured to switch a voltage of at least 200 volts. The output driver includes a high-side output transistor. The pulse generator is configured to generate an on pulse at a leading edge of an input signal received at an input terminal of the level shifter and to generate an off pulse at a trailing edge of the input signal. The high-side gate driver is configured to drive the high-side output transistor. The high-side gate driver is coupled to an on pulse signal line that conducts the on pulse and coupled to an off pulse signal line that conducts the off pulse. The high-side gate driver includes a blocking circuit comprising a plurality of transistors configured to inhibit a change in state of the drive signal to the high-side output transistor based on simultaneous assertion of signals on both the on pulse signal line and the off pulse signal line, and based on simultaneous negation of signals on both the on pulse signal line and the off pulse signal line.